A semiconductor device, such as a transistor, may include contacts that connect a diffusion region or transistor node (e.g., source or drain) in the substrate to a metal layer. These contacts may be located adjacent to the transistor gate. Contacts may affect the manufacturing yield and device performance of the transistor. Unfortunately, an attempt to increase manufacturing yield may result in diminished device performance. For example, a contact with a larger bottom critical dimension (CD), located near the diffusion region in the substrate, may provide higher performance. However, a smaller CD in the contact near the top of the gate, at the gate height, might result in fewer contact to gate (CTG) shorts. Fewer such shorts may result in a better manufacturing yield. Thus, increasing the size of a contact may increase device performance but at the expense of manufacturing yield.